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78m6610+lmu energy measurement processor for load monitoring units for pricing, delivery, and ordering information, please contact maxim direct at 1- 888- 629 - 4642, or visit maxim integrated?s website at www.maximintegrated.com. 19 - 6573 ; rev 0; 1 /1 3 general description the 78m6610+lmu is an energy measurement processor (emp) for load monitoring and control of any 2- wire single - phase or 3 - wire split - phase (120/180 ) ac circuit . it provides flexible sensor configuration of four analog inputs and numerous host interface options for easy integration into any system architecture . the internal 24- bit processor and field upgradeable firmware performs all the necessary signal process ing, compensation , and data formatting for accurate real - time measurement . energy accumulation, alarm monitoring, and fault detection schemes minimize the overhead requirements of the host interface and/or network . the integrated flash memory also provides for non volatile storage of input configurations and calibration coefficients. applications ? building automation systems (commercial, industrial) ? inverters and renewable energy systems ? level 1 and 2 ev charging systems ? g rid - friendly appliances and smart plugs features ? four configurable analog inputs for monitoring any single - phase circuit (2/3 -w ire) ? supports current transformers (ct) and resistive shunts ? flexible spi , i 2 c, or uart interface options with configurable i/o p ins for alarm signaling, address pins, or user c ontrol ? nonvolatile s torage of c alibration and configuration parameters ? small 24 - tqfn p ackage and reduced bill of m aterials ? internal or external oscillator timing references ? quic k calibration routines minimize manufacturing (system) cost measurement processor ram flash uart spi i 2 c digital i/o single converter front end mux adc 78m 6610 + lmu voltage sensor (s) current sensor (s) host interface load relay (s)
78m6610+lmu data sheet 2 rev 0 tab le of contents electrical specifications ............................................................................................................................. 5 absolute maximum ratings .................................................................................................................. 5 recommended external components .................................................................................................. 5 recommended operating conditions ................................................................................................... 5 performance specifications .................................................................................................................. 6 input logic levels ....................................................................................................................... 6 output logic levels .................................................................................................................... 6 supply current ............................................................................................................................ 6 crystal oscillator ......................................................................................................................... 6 internal rc oscillator .................................................................................................................. 6 adc converter, v 3p3 referenced ................................................................................................ 7 timing specifications ............................................................................................................................ 8 reset ........................................................................................................................................... 8 spi slave port ............................................................................................................................. 8 i 2 c slave port (note 1) ................................................................................................................ 9 pin configuration ...................................................................................................................................... 10 package in formation ........................................................................................................................... 11 on - chip resources overview ................................................................................................................. 12 ic block diagram ................................................................................................................................ 12 clock management ............................................................................................................................. 13 power - on and reset circuitry ............................................................................................................ 14 watchdog timer .................................................................................................................................. 14 analog front - end and conversion ..................................................................................................... 15 24- bit energy measurement processor (emp) ................................................................................... 15 flash and ram .......................................................................................................................... 15 multipurpose dios .............................................................................................................................. 15 communicat ion interface .......................................................................................................... 15 functional description and operation .................................................................................................... 16 measurement interface ....................................................................................................................... 16 afe in put multiplexer ................................................................................................................ 16 high pass filters and offset removal ...................................................................................... 17 gain correction ......................................................................................................................... 18 die temperature compensation ............................................................................................... 18 phase compensation ................................................................................................................ 19 voltage input configuration ....................................................................................................... 20 current input configuration ....................................................................................................... 23 data refresh rates ............................................................................................................................ 26 scaling registers ................................................................................................................................ 26 calibration ........................................................................................................................................... 27 voltage and current gain calibration ....................................................................................... 27 offset calibration ...................................................................................................................... 27 die temperature calibration ..................................................................................................... 27 voltage channel measurements ........................................................................................................ 28 quadrature voltage ................................................................................................................... 28 voltage frequency .................................................................................................................... 28 peak voltage ............................................................................................................................. 28 rms voltage ............................................................................................................................. 28 current channel measurements ......................................................................................................... 29 peak current ............................................................................................................................. 29 rms current ............................................................................................................................. 30 crest factor ............................................................................................................................... 30 power calculations ............................................................................................................................. 31 active power (p) ....................................................................................................................... 31
78m6610+lmu data sheet 3 rev 0 reactive pow er (q) ................................................................................................................... 32 apparent power (s) ................................................................................................................... 32 power factor (pf) ..................................................................................................................... 32 fundamental and harmonic calculations ........................................................................................... 33 energy calculations ............................................................................................................................ 34 bucket size for energy counters .............................................................................................. 34 min/max tracking ................................................................................................................................ 36 alarm monitoring ................................................................................................................................ . 37 status regis ters .................................................................................................................................. 39 digital io functionality ........................................................................................................................ 40 dio polarity ............................................................................................................................... 40 multipurpose (mp) pins ............................................................................................................. 41 comman d register ............................................................................................................................. 42 normal operation ...................................................................................................................... 42 calibration command ............................................................................................................... 42 save to flash command ........................................................................................................... 43 control register .................................................................................................................................. 43 configuration register ........................................................................................................................ 43 register access ........................................................................................................................................ 44 data types .......................................................................................................................................... 44 register locations .............................................................................................................................. 45 serial interfaces ........................................................................................................................................ 49 uart interface ................................................................................................................................... 49 rs - 485 support ........................................................................................................................ 49 device address configuration ................................................................................................... 50 ssi protocol description ........................................................................................................... 51 spi interface ....................................................................................................................................... 55 i 2 c interface ........................................................................................................................................ 58 device address configuration ................................................................................................... 58 bus characteristics ................................................................................................................... 59 device addressing .................................................................................................................... 59 write operations ....................................................................................................................... 60 read operati ons ....................................................................................................................... 61 ordering information ................................................................................................................................ 62 contact information .................................................................................................................................. 62 revision history ........................................................................................................................................ 63
78m6610+lmu data sheet 4 rev 0 table of figures figure 1. spi timing ..................................................................................................................................... 8 figure 2. i 2 c timing ...................................................................................................................................... 9 figure 4. package outline ........................................................................................................................... 11 figure 5. block diagram .............................................................................................................................. 12 figure 6. crystal connections ..................................................................................................................... 13 figure 7. reset connections ...................................................................................................................... 14 figure 8. afe input multiplexer .................................................................................................................. 16 figure 9. voltage input configuration ......................................................................................................... 20 figure 10. voltage computation ................................................................................................................. 20 figure 12. voltage input flowchart ............................................................................................................. 22 figure 13. current input configuration ....................................................................................................... 23 figure 14. current computation ................................................................................................................. 23 figure 15. current configuration examples ................................................................................................ 24 figure 16. current input flowchart ............................................................................................................. 25 figure 17. peak voltage computation ........................................................................................................ 28 figure 18. rms voltage computation ........................................................................................................ 28 figure 19. peak current computation ........................................................................................................ 29 figure 20. rms current computation ........................................................................................................ 30 figure 21. active power computation ........................................................................................................ 31 figure 22. reactive power computation .................................................................................................... 32 figure 23. apparent power computation .................................................................................................... 32 figure 24. min/max tracking ....................................................................................................................... 36 figure 25. voltage sag ............................................................................................................................... 38 figure 26. relay timing .............................................................................................................................. 41 figu re 27. rs - 485 interface ........................................................................................................................ 49 figure 28. device address configuration ................................................................................................... 50 figure 29. ssi protocol ............................................................................................................................... 51 figu re 30. master packet structure ............................................................................................................ 51 figure 31. spi interface .............................................................................................................................. 55 figure 32. spi timing continuous clock .................................................................................................... 57 figure 33. spi timing gapped clock ......................................................................................................... 57 figure 34. i 2 c interface ............................................................................................................................... 58 figure 35. i 2 c device address .................................................................................................................... 58 figure 36. i 2 c bus characteristics .............................................................................................................. 59 figure 37. i 2 c device addressing ............................................................................................................... 59 figure 38. write operation ? single register .............................................................................................. 60 figure 39. write operation ? multiple registers .......................................................................................... 60 figure 40. read operation .......................................................................................................................... 61 figure 41. setting read address ................................................................................................................ 61 figure 42. reading multiple registers ........................................................................................................ 61
78m6610+lmu data sheet 5 rev 0 electrical specifications absolute maximum ratings (all voltages with respect to ground.) supplies and ground pins: v 3p3d , v 3p3a - 0.5v to + 4.6 v gndd, gnda - 0.5v to +0.5 v analog input pins: a0, a1, a2, a3, a4, a5 - 10ma to +10ma - 0.5 v to (v 3p3 + 0.5 v) oscillator pins: xin, xout - 10ma to +10ma - 0.5v to + 3.0 v digital pins: ifc0, ifc1, ssb/dir/scl, sdo/tx/ sdao , sdi/rx/ sdai , reset , sp ck/ addr0 , mp10 , mp0, mp4, mp6/addr1 , mp7 - 30 ma to + 30 ma, - 0.5 v to (v 3p3d + 0.5 v) digital pins c onfigured as i nputs - 10 ma to + 10 ma, - 0.5 v to + 6v temperatures: operating junction temperature ) peak, 100 ms +140 c c ontinuous + 125c storage t emperature range - 45c to +165 c lead t emperature (soldering, 10s) + 260c soldering temperature (reflow) 0 c esd s tress on a ll p ins 4 kv recommended external components name from to function value unit s xtal xin xout 20.000mhz 20.000 mhz cxs xin gnd d load capacitor for crystal (exact value depends on crystal specifications and parasitic capacitance of board) 18 10% pf cxl xout gnd d 18 10% pf recommended operating conditions parameter condition s min typ max unit s 3.3v supply voltage (v 3p3 ) normal o peration 3.0 3.3 3.6 v operating temperature - 40 C +85 c
78m6610+lmu data sheet 6 rev 0 performance specifications note that production tests are performed at room temperature. input logic levels parameter condition s min typ max unit s digital high - level input voltage (v ih ) 2 ? ? v digital low - level input voltage (v il ) ? ? 0.8 v output logic levels parameter condition s min typ max unit s digital high - level output voltage (v oh ) i load = 1 ma v 3p3 - 0.4 C C v i load = 10ma v 3p3 - 0.6 C C v digital low - level output voltage (v ol ) i load = 1 ma 0 ? 0.4 v i load = 10 ma ? ? 0.5 v supply current parameter condition s min typ max unit s v 3p3d and v 3p3a c urrent (c ompounded) normal o peration , v 3p3 = 3.3v ? 8.1 10.3 ma crystal oscillator parameter condition s min typ max unit s xin to xout capacitance (note 1) ? 3 ? pf capacitance to gnd d (note 1) xin ? 5 ? pf xout ? 5 ? note 1: guaranteed by design ; not subject to test. internal rc oscillator parameter condition s min typ max unit s nominal frequency ? 20.000 ? mhz accuracy v 3p3 = 3.0v, 3.6v ; t emperature = - 40 c to +85 c ? 1.5 ? %
78m6610+lmu data sheet 7 rev 0 adc converter, v 3p3 referenced lsb values do not include the 9 - bit left shift at emp input. parameter condition s min typ max unit s usable input range (v in - v 3p3 ) - 250 ? + 250 mv peak thd (first 10 h armonics ) v in = 65 hz, 64 kpts fft, blackman - harris window ? - 85 ? db input impedance v in = 65 hz 30 ? 90 k temperature c oefficient of input impedance v in = 65 hz (note 1) ? 1.7 ? /c adc gain error vs . %power supply variation 3.3/33100 /357 10 6 apv vnv nout in pk ? ? v in = 200mv pk, 65 hz ; v 3p3 = 3.0v, 3.6v ? 50 ? ppm/% input offset (v in - v 3p3 ) - 10 + 10 mv 1 guaranteed by design ; not subject to test.
78m6610+lmu data sheet 8 rev 0 timing specifications reset parameter condition s min typ max unit s reset pulse fall time (note 1) ? 1 ? s reset pulse w idth (note 1) ? 5 ? s spi slave port parameter conditions min typ max units spck cycle time ( t spicyc ) 1 C C s enable lead time (t spilead ) 15 C C ns enable lag time (t spilag ) 0 C C ns spck pulse width (t spiw ) high 250 C C ns low 250 C C ssb to f irst spck f all (t spisck ) ignore if spck is low when ssb falls (note 1) C 2 C ns disable t ime (t spidis ) (note 1) C 0 C ns spck to data out (sdo) (t spiev ) C C 25 ns data input setup time (sdi) (t spisu ) 10 C C ns data input hold time (sdi) (t spih ) 5 C C ns note 1: guaranteed by design, not subject to test. msb out lsb out msb in lsb in t spicyc t spilead t spilag t spisck t spih t spiw t spiev t spiw t spidis ssb spck sdi sdo t spisu figure 1. spi timing
78m6610+lmu data sheet 9 rev 0 i 2 c slave port (note 1) parameter conditions min typ max units bus idle (free) time between transmissions ( stop/start ) (t buf ) 1500 C C ns i 2 c i nput fall time (t icf ) (note 2) 20 C 300 ns i 2 c i nput rise time (t icr ) (note 2) 20 C 300 ns i 2 c start or r epeate d start condition hold time (t sth ) 500 C C ns i 2 c s tart or r epeate d start condition setup time (t sts ) 600 C C ns i 2 c clock high time (t sch ) 600 C C ns i 2 c clock low time (t scl ) 1300 C C ns i 2 c serial data setup time (t sds ) 100 C C ns i 2 c serial data hold time (t sdh ) 10 C C ns i 2 c valid data time (t vda ) : scl lo w to sda output v alid ack si gnal from scl l ow to sda ( out) low C C 900 ns note 1: guaranteed by design, not subject to test note 2: dependent on bus capacitance. t buf stop start t sth t sch t scl scl t icr t icf t icr t icf sda t sds t sdh t vda t sps t sts stop condition repeat start condition figure 2. i 2 c timing
78m6610+lmu data sheet 10 rev 0 pin configuration figure 3. qfn package pinout pin signal function pin signal function 1 a5 analog input (negative) 13 sdi/rx/ sda i spi data in / uart rx/ i 2 c data in 2 gnda g round (analog) 14 spck/ addr0 spi clock / mpio 3 ifc0 ifc1/spi (1 = ifc1 ; 0 = spi) 15 mp0 multi p urpose digital i/o 4 mp7 multi p urpose digital i/o 16 mp10 multi p urpose digital i/o 5 mp6/addr1 multi p urpose digital i/o 17 ifc1 i 2 c/uart (1 = i 2 c;0 = uart) 6 ssb/dir/ scl slave select (spi) / rs - 485 tx - rx / i 2 c serial clock 18 reset active - low reset input 7 mp4 multi p urpose digital i/o 19 a0 analog i nput 8 v 3p3d 3.3v dc supply (digital) 20 a1 analog i nput 9 xin crystal oscillator driver input 21 v 3p3a 3.3v dc supply (analog) 10 xout crystal oscillator driver output 22 a2 analog i nput (positive) 11 gndd g round (digital) 23 a3 analog i nput (negative) 12 sdo/tx/ sda o spi data out/ uart tx/ i 2 c data out 24 a4 analog i nput (positive) reset gnda a5 ifc 0 mp 7 mp 0 mp 10 ssb / dir / scl mp 6/ addr 1 6 5 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 sdi / rx / sdai sdo/tx/sdao ( top ) xin xout v 3p3d a4 a3 a2 v 3p3a a1 a0 spck / addr 0 78 m6610 +lmu ifc 1 gndd mp4
78m6610+lmu data sheet 11 rev 0 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 24 t qfn t244 4+4 21 - 0139 90 - 0022 figure 4. package outline
78m6610+lmu data sheet 12 rev 0 on - chip resources overview the 78m6610+lmu device integrates all the hardware blocks required for accurate ac power and energy measurement. included on device are: ? o scillator circui ts and clock management logic ? power - on reset, watchdog timer, and reset circuitry ? high - accuracy analog front - end (afe) with trimmed voltage reference and temperature sensor ? 24- bit energy measurement processor (emp) with ram and flash memory ? serial uart, spi, i 2 c interfaces and multipurpose d igital i/o ic block diagram the following is a block diagram of the hardware resources available on the 78m6610+lmu. xtal osc mux 9 xin 10 xout 8 fir vref vbias gen ibias gen mux control info. block flash 4kx16 program memory emp clock gen 11 uart temp sense 12 13 3 17 16 15 6 spck/addr0 ce data ram 512x24 i 2 c 18 adc 16 ck20m spi rc osc ck sel 24 b data bus 14 timers watch dog program bus io mux trim bits 21 v 3p3a 2 2.5v reg. 2.5v v3p3 div mpy temp log. 4 gnda 24 a4 23 a3 22 a2 20 a1 19 a0 sdi/rxd/sdai sdo/txd/sdao ssb/dir/scl ifc0 ifc1 mp10 mp0 mp7 7 5 mp4 mp6/addr1 1 a5 v 3p3d gndd reset figure 5. block diagram
78m6610+lmu data sheet 13 rev 0 clock management the device can be clocked by either a trimmed internal rc oscillator or by oscillator circuitry that relies on an external crystal. the internal rc oscillator provides an accurate clock source for uart baud rate generation. only time based calculations such as line frequency and watt - hour (energy) are affected by clock accuracy . the chip hardware automatically handles the clock sources logic and distributes the clock to the rest of the device. upon reset or pow er - on, the device will utilize the internal rc oscillator circuit for the first 1024 clock cycles, allowing the external crystal adequate time to start - up . the device will then automatically select the external clock , if available . it will also automatically switch back to the internal oscillator in the event of a failure with the external oscillator. this condition is also monitored by the processor and available to the user in the status register. the 78m6610+lmu external clock circuitry requires a 20.000mhz crystal. the circuitry includes two 18pf ceramic capacitors. the figure below shows the typical connection of the external crystal. this oscillator is self biasing and therefore an external resistor should not be connected across the cryst al. xin xout 18pf 18pf 20.000mhz 78m6610+lmu figure 6. crystal connections a n external 20mhz system clock signal can also be utilized instead of the crystal. in this case , the external clock should be connected to the xout pin while the xin pin should be connected to gndd. alternatively, if no external crystal or clock is utilized, the xout pin should be connected to gndd and the xin pin left unconnected.
78m6610+lmu data sheet 14 rev 0 power - on and re set circuitry an on - chip power - on reset (por) block monitors the supply voltage (v 3p3d ) and initializes the internal digital circuitry at power - on. once v 3p3d is above the minimum operating threshold, the por circuit triggers and initiates a reset sequence. it will also issue a reset to the digital circuitry if the supply voltage falls below the minimum operating level. in addition to the internal sources, a reset can be forced by applying a low level to the reset pin . if the reset pin is pulled low, all digital activities in the device stop, except the clock management circuitry and oscillators, which continue to run. the external reset input is filtered to prevent spurious reset events in noisy environments. the reset does not occur until reset has been held low for at least 1 s. once initiated, the reset mode persists until the reset is set high and the reset timer times out (4096 clock cycles). at the completion of the reset sequence, the internal reset is released and the processor (emp) begins executing from address 0. if not used, the reset pin can be connected either directly or through a pullup resistor to v 3p3d supply. a simple connection diagram is shown below . gndd v 3p3d reset 1nf 10k v 3p3 gnd manual reset switch gndd v 3p3d reset v 3p3 gnd 78m6610+lmu 78m6610+lmu a) external reset connection example b) unused reset connection example figure 7. reset connections watchdog timer a watchdog timer (wdt) block detects any software processing errors. t he software periodically refreshes the free - running watchdog timer to prevent it from timing out. if the wdt times out, it is an indication that software is no longer being executed in the intended sequence; thus, a system reset is initiated.
78m6610+lmu data sheet 15 rev 0 analog front - end and conversion the analog front - end ( afe) include s an input multiplexer, optional pre - amp lifier gain stage, d elta -s igma a/d c onv erter, bias current references, voltage references, temperature sensor, and several voltage fault comparators. analog inputs up to four external sensors can be connected to the 78m6610+lmu . two single - ended inputs are avai lable for voltage sensors and two differential pairs are available for connecting current sensors. although the current inputs are differential inputs, a common - mode voltage of less than v 3p3a 25 mv is recommended in order to utilize the available dynamic range . the full - scale signal level that can be applied t o the analog input pins is v 3p3a 250 mvpk. considering a sinusoidal ac waveform, the maximum rms voltage applied to the inputs pins is: rmsmax = 250 ???? 2 = 176 . 78mvrms delta -s igma a/d converter a second - order d elta -s igma converter digitizes the analog inputs. the converted data is then processed through a fir filter . voltage reference the device includes an on - chip precision bandgap voltage reference that incorporates auto - zero techniques as well as production trims to minimize errors caused by component mismatch and drift . the voltage reference is digitally compensated over temperature. die temperature measurement the device includes an on- chip die temperature sensor used for digital compensation of the voltage reference . it is also used to report temperature information to the user . 24- bit energy measurement processor (emp) the 78m6610+lmu integrates a dedicated 24- bit signal processor that performs the entire digital signal processing necessary for energy measure ment, alarm generation, calibration , compensation, etc. re fer to section 2 for a description of functionality and operations. flash and ram the 78m6610+lmu includes 8kb of on - chip flash memory. the flash memory primarily contains program code, but also stores calibration data and defaults for select nonvolatile configuration registers. the device also includes 1.5kb of on - chip ram which contains the values of input and output registers and is utilized by the processor for its operations. multi p urpose dios there are a total of eleven digital input/outputs (dios) on the 78m6610+lmu de vice . some are dedicated to serial interface communications and configuration . others are multipurpose i/o that can be used as a s imple output under user control or routed to special purpose internal signals like alarm signaling and relay control. communication interface the 78m6610+lmu includes three communication interfaces: uart, spi, and i 2 c . since the i/o pins are shared, only one mode is supported at a time. interface configuration and address pins are sampled at power - on or reset to determine which interface will be active and to set device addresses.
78m6610+lmu data sheet 16 rev 0 functional description and operation t his section describes the operation and configuration of the 78m6610+lmu . it includes the flow of measurement data, relevant calculations, alarm monitoring , i/o control, and user configuration s. measurement interface the 78m6610+lmu incorporates a flexible measurement interface for simplified integration into any single - phase system . this section describes the configuration and signal conditioning of the analog inputs. s ett ings and calibration parameters described in this section can be saved to flash memory and automatically initialized upon power on or reset . afe input multiplexer the 78m6610+lmu samples four ( 4) external sensors with an effective sample rate of 4ksps for each multiplexer slot . two analog input pin s are defined as single ended voltage inputs with t he other four analog input pin s defined as a pair of differential current inputs . sinc 3 decimator a0 cross- point ? modulator precision reference f adc adc a1 a2 a3 a4 a5 mux control s0 s1 s2 s3 signal processor results s0 s2 s1 s3 p n p n figure 8. afe input multiplexer sensor slot analog input pins input type s0 a0 voltage s1 a2 (pos) and a3 (neg) current s2 a1 voltage s3 a4 (pos) and a5 (neg) current
78m6610+lmu data sheet 17 rev 0 high pass filters and offset removal offset registers for each analog input contain values to be subtracted from the raw adc outputs for the purpose of removing inherent system dc offsets from any calculated power and rms values . these registers are signed fixed point numbers with a possible range of - 1.0 to 1 - lsb . they default to 0 and can be manually changed by the user or integrated offset calibration routines. register description s1_off s current input s 1 offset calibration s0_off s voltage input s0 offset calibration s3_off s current input s3 offset calibration s2_off s voltage input s2 offset calibration alternatively, the user can enable an integrated high pass filter (hpf) to dynamically update the offset registers every accumulation interval. during each accumulation interval (or low - rate cycle) the hpf calculates the median or dc average of each input . adjustable coefficients determine what portion of the measured offset is combined with the previous offset value. hpf_coef_x registers contain signed fixed point numbers with a usable ran ge of 0 to 1 - lsb (0.99999), negative values are not supported . by default, they are initialized to 0.5 (0x400000) meaning the new offset value will come from one- half of the measured offset and one - half will come from the previous offset value. setting them to 1.0 (0x7fffff) causes the entire measured offset to be applied to the offset register enabling lump - sum offset removal. setting them to zero disables any dynamic update of the offset registers by the hpf. register description hpf_coef_i hpf coefficient for s1 and s3 current inputs hpf_coef_v hpf coefficient for s0 and s2 voltage inputs to allow the dc component of the load current to be included in the measurement (i.e. half - wave rectified current waveforms), the hpf _coef_i coefficients must be set to zero. using the offset calibration routine will automatically set the filter coefficients to zero to disable the hpf.
78m6610+lmu data sheet 18 rev 0 gain correction the system (sensors) and the 78m6610+lmu device inherently have gain errors that can be corrected by using the gain registers . these registers can be directly accessed and modified by an external processor or automatically updated by an integr ated self calibration routine. input gain register s are signed fixed point numbers with the binary point to the left of bit 21. they are set to 1.0 by default and have a usable range of 0 t o 4 - lsb, negative values are not supported . the gain equation for each input slot can be described as sx = sx * sx_ gain . register description s0_gain voltage input s0 gain calibration. s1_gain current input s1 gain calibration s2_gain voltage input s2 gain calibration. s3_gain current input s3 gain calibration die temperature compensation the 78m6610+lmu has an on - chip temperature sensor that can be used by the signal processor for monitoring the voltage reference error and made available to the user in the temp c register. setting the temperature compensation (tc) bit in the command register allows the firmware to further adjust the system gain based on measured die temperature. die temperature offset is typically calibrated by the user during the calibration stage . die temperature gain is set to a factory default value for most applic ations , but can be adjusted by the user. register description t_offs die temperature offset calibration. t_gain die temperature slope calibration. set by factory . voltage reference gain adjustment the on- chip precision bandgap voltage reference incorporates auto - zero techniques as well as production trims to minimize errors caused by component mismatch and drift . it can be assumed that the part is trimmed at 22c to produce a uniform voltage reference gain at that temperature . the voltage reference is digitally compensated over changes in measured die temperature using a quadratic equation .
78m6610+lmu data sheet 19 rev 0 phase compensation phase compensation registers are used to compensate for phase errors or time delays between the voltage input source and respective current source that are introduced by the off - chip sensor circuit . the user configurable registers are signed fixed point numbers with the binary point to the left of bit 21 . values are in units of high rate (4 kh z) samp le delays so each integer unit of delay is 250 s with a total possible delay of 4 samples (roughly 20 at 60hz). register description phasecomp1 phase (delay) compensation for s1 input current phasecomp3 phase (delay) compensation for s3 input current example: to compensate a phase error of 277.77s (or 6 at 60hz) introduced by a current transformer (ct) it is necessary to enter the following: ?? ??? ???????????? = ?? ??? ????? 1 ?????? ???? ?? ??? ???? ? ??????? = 277? ?6 1 4000 = 1. 111 the value to be entered in the phase compensation register is therefore: ????? = 1. 111 ? 2 21 = 2330169 = 0x238e39
78m6610+lmu data sheet 20 rev 0 voltage input configuration the 78m6610+lmu supports multiple analog input configurations for determining the three potential voltage sources in a split - phase circuit . the device measure s the voltage difference between any two references and use s this information to derive the v oltages va, vb, and vc as shown below. conductor a conductor n conductor b va vb vc + + + - - - figure 9. voltage input configuration each calculated voltage source (va , vb, and vc ) is derived from the following user configurable function of the voltage input multiplexer slots (s0, s2) and three pairs of multiplier values (m0, m2) . this function derives source voltages va, vb, and vc by summing s0 x m0 and s2 x m2. m0 + m2 vx s0 s2 figure 10 . voltage computation the user sets the multiplier values m0 and m2 for each voltage source in the config register using the model where a one (1) value adds the input, a two (2) value adds two of the input, a minus one ( - 1) value subtract the input, a zero (0) value does not include the input. config bits 19:18 17:16 15:14 13:12 11: 10 9: 8 multiplier m2 m0 m2 m0 m2 m0 source vc vb va there are four choices for every m value as shown below. multiplier bits 00 01 10 11 m (multiplier) value -1 0 1 2 the output registers va, vb , and vc are automatically scaled by a factor of 0.5 if m0 and m2 are both nonzero. for example, by setting the multiplier bits as follows: ?? = +1 ? ? 0 ? 1 ? ? 2 the effective content of the vc register would result in: ?? = ( +1 ? ? 0 ) + ( ?1 ? ? 2) 2 this scaling is done to prevent the output register from overflowing.
78m6610+lmu data sheet 21 rev 0 two example configurations are shown below. for determining the sign of s0 or s2 measurements, one should note that results for single ended inputs are referenced to v 3p3 . conductor a conductor n conductor b 78m6610+lmu a1 v 3p3 a0 v a = +1*s0 +0*s2 v b = +0*s0 +1*s2 v c = +1*s0 -1*s2 conductor a conductor n conductor b 78m6610+lmu a1 v 3p3 a0 v a = -1*s0 +0*s2 v b = +1*s0 -1*s2 v c = +0*s0 -1*s2 s0 s2 s0 s2 figure 11 . example voltage configurations
78m6610+lmu data sheet 22 rev 0 voltage input flowchart the figure below illustrates the computation al flowchart for va, vb, and vc . the values for voltage input configuration register can be saved in flash memory and automatically restored at power - on or reset. x gain_ajust delay compensation 2, 1, -1, 0 config x delay compensation 2, 1, -1, 0 + va s0 s2 x 2, 1, -1, 0 config x 2, 1, -1, 0 + vb x x 2, 1, -1, 0 config x 2, 1, -1, 0 + vc x s0_gain hpf_coef_v x s2_gain x s0_offs s2_offs hpf hpf figure 12 . voltage input flowchart
78m6610+lmu data sheet 23 rev 0 current input configuration the 78m6610+lmu supports multiple analog input configurations for determining the two load currents in a split - phase ac circuit . the device measures the current of any two conductors and uses this information to derive the load currents shown below. conductor a conductor n conductor b i b ia= - i b - i n ib= - i a - i n i n i a figure 13 . current input configuration each calculated load current (ia and ib) is derived from the following function of the current input slots (s1 and s3) and 2 pairs of multiplier values (m1 and m3) . this function derives source currents ia and ib by summing s1 x m1 and s3 x m3. m1 + m3 ix s1 s3 figure 14 . current computation the user sets the multiplier values for each current source in the config register using the model where a one (1) value adds the input, a two (2) value adds two of the input, a minus one ( - 1) value subtract the input, a zero (0) val ue does not include the input. config bits 7: 6 5: 4 3: 2 1: 0 multiplier m3 m1 m3 m1 source ib ia there are four choices for every m value as shown below. bit v alues 00 01 10 11 m (multiplier) value -1 0 1 2 the output registers ia and ib are automatically scaled by a factor of 0.5 if m1 and m3 are both non zero. for example, by setting the multiplier bits as follows: ?? = +1 ? ? 1 ? 1 ? ? 3 the effective content of the vc register would result in: ?? = ( +1 ? ? 1 ) + ( ?1 ? ? 3) 2 this scaling is done to prevent the output register from overflowing.
78m6610+lmu data sheet 24 rev 0 current configuration examples 78m6610+lmu a3 a2 a4 a5 conductor a conductor n conductor b 78m6610+lmu i a = +1*s1 +0*s3 i b = +0*s1 +1*s3 a3 a2 a5 i b a4 i n conductor a conductor n conductor b i a i n i b i a = +1*s1 +0*s3 i b = -1*s1 -1*s3 i a s1 s3 s1 s3 figure 15 . current configuration examples pre -a mp by default, the full - scale signal that can be applied to the current inputs is v 3p3a 250mvpk (176.78mv rms ) . this setting provides the widest dynamic range and is recommended for most applications. for applications requiring a much lower value shunt resistor, an optional pre - amplifier with a n 8x gain is included for the current inputs . the maximum input signal applied to the current inputs in this case would be is v 3p3a 31.25 mvpk . config[21:20] 00 01 10 11 8x gain enable none s1 s3 both the gain is set by a ratio of internal resistors with one of the resistors in series from the input pad to the pre - amp itself. as such, the device must only be directly connected to a shunt with minimal resistance when using the pre - amp.
78m6610+lmu data sheet 25 rev 0 current input flowchart the figure below illustrates the computational flowchart for ia and ib . the values for current input configuration register can be saved in flash memory and automatically restored at power - on or reset. x 2, 1, -1, 0 config x 2, 1, -1, 0 + ia s1_gain delay compensation x 2, 1, -1, 0 config x 2, 1, -1, 0 + ib hpf hpf hpf_coef_i config x8 x s1 s3_gain delay compensation config x8 x s3 gain_adj x x s1_off s3_off figure 16 . current input flowchart
78m6610+lmu data sheet 26 rev 0 data refresh rate s instantaneous voltage, current, power , and quadrature measurement results are updated at the sample rate of 4ks/s and are generally not useful unless accessed with a high speed interface such as spi . the cycle register is a 24 - bit counter that increment s every high - rate sample update and reset s when low - rate results are updated. low - rate results, updated at a user configurable rate, are typically used and more suitable for most applications . the frame register is a counter that increments every accumulation interval . a data ready indicator in the status register indicates when new data is available . the high - rate samples are averaged to produce one low - rate result (know n as an accumulation interval), increasing their accuracy and repeatability. low - rate results include rms voltages and currents, frequency, power , energy, and power factor . the accumulation interval can be based on a fixed number of adc samples or locked to the incoming line voltage cycles. if line lock is disabled, the accumulation interval defaults to a fixed time interval defined by the number of samples defined in the samples register (default of 400 samples or 0.1 seconds). when the line - lock bit in the command register is set, and a valid ac voltage signal is present, the actual accumulation interval is stretched to the next positive zero crossing of the reference line voltage after the defined number of samples has been reached . if there is not a valid ac signal present and line lock is enabled, there is a 100 sample timeout implemented that would limit the accumulation interval to samples+100. the divisor register records the actual duration (number of high- rate samples) of the last low - rate interv al whether or not line - lock is enabled. two bits in the config register allow the user to select the reference voltage slot for deriving zero - crossing detection and line frequency. config[23:22] 00 01 10 11 voltage reference s0 s2 s0 - s2 s0+s2 scaling registers most measurement data is reported in binary full - scale units with a value range of - 1.0 to 1 - lsb . all full scale register readings correspond to the max analog input of 250mvpk (or 31.25mvpk with 8x gain) . as an example, if 230v - peak at the input to the voltage divider gives 250mv - peak at the chip input, one would get a full scale register reading of 1 - lsb (0x 7fffff) for in stantaneous voltage. similarly , if 30apk at the sensor input provides 250mv - peak to the chip input, a full scale register value of 1 - lsb (0x7fffff) for instantaneous current would correspond to 30 amps . full scale watts correspond to the result of full scale current and voltage so , in this example, full scale watts is 230 x 30 or 6900 watts. n on vola tile registers (ifscale and vfscale) are provided for storing the real - world current and voltage levels that apply to the full scale register readings for any given board design . any host application can then format the measurement results to any data form at as needed . the usage of these nonvolatile scratchpad registers is user defined and their content has no effect on the internal operations of the device. frequency data has a range of 0 to +32768hz less one lsb (format s15.8). temperature data has a fixed scaling with a range of - 65536c to +65536c less one lsb (format s16.7).energy data scaling is described in detail in section 2.10.
78m6610+lmu data sheet 27 rev 0 calibration the 78m6610+lmu provides integrated calibration routines to modify gain and offset coefficien ts. the user can set up and initiate a calibration routine through the c ommand r egister . when in calibration mode , the line - lock bit should be set for best results. the calibration routines will write the new coefficients to the relevant registers . the user can then save the new coefficients into flash memory as defaults using the flash access command in the c ommand r egister . see the command register section for more information on using commands. voltage and current gain calibration in order to calibrate the gain parameters for voltage and current channels, a reference ac signal must be applied to the channel to be calibrated. the rms value corresponding to the applied reference signal must be entered in the relevant target register ( vtarget , itarget ). considering calibration is done with low - rate rms results , the value of the target register should never be set to a value above 70.7% of full - scale . initially, the value of the gain is set to unity for the selected channels. rms values are then calculated on all inputs and averaged over the number of measurement cycles set by the calcycs register . the new gain is calculated by dividing the appropriate target register value by the averaged measured value. the new gain is then written to the select gain registers unless an error occurred. on a successful calibration, the command bits are cleared in the command register, leaving only the system setup bits. in case of a failed calibration, the bit in the command r egister corresponding to the failed calibration is left set. offset calibration to calibrate offset, all signals should be removed from all analog inputs although it is possible to do the calibration in the presence of ac signals. in the command, the user also specifies which channel(s) to calibrate. target registers are not used for offset calibration. during the calibration process, each input is accumulated over the entire calibration interval as specified by the calcycs register. the result is divided by the total number of samples and written to the appropriate offset register if selected in the calibration command. using the offset calibration command will set the respective hpf coefficients to zero thereby fixing the sx_offs offset registers to thei r calibrated values. upon completion of calibration, only the 0xcaxxxx bits of the command register are cleared. die temperature calibration to re - calibrate the on - chip temperature sensor offset , the user must first write the known chip temperature to the t_target register . next, the user initiates the temperature calibration command in the c ommand r egister . this will update the t_offs offset parameter with a new offset based on the known temperature supplied by the user . the t_gain gain register is set by the factory and not updated with this routine. the range of the die temperature registers is - 128 to +128 - lsb degrees celsius.
78m6610+lmu data sheet 28 rev 0 voltage channel measurements i nstantaneous and quadrature voltage measurements are updated every sample while rms voltage and peak voltage are updated every accumulation interval ( n samples) . an ac voltage frequency measurement is also updated every low - rate interval. register description time s cale va vb vc instantaneous voltage @ time t 1 sample vqa vqb quadrature voltage @ time t - 90 freq ac voltage frequency 1 interval va_peak vb_peak peak voltage in last interval va_rms vb_rms vc_rms rms voltage of last interval quadrature voltage the quadrature voltage is instantaneous voltage that is phase shifted (delayed) 90 from the respective input voltage. voltage frequency this output is a measurement of the fundamental frequency of the referenced ac voltage source with a range from 0hz to 128hz - lsb . this is a single reading per device . peak voltage this output is a capture of the largest magnitude instantaneous voltage source sample during the previous accumulation interval. vx_peak instantaneous voltage (vx) abs max maximum figure 17 . peak voltage computation rms voltage t he 78m6610+lmu reports true rms measurements for each input. an rms value is obtained by performing the sum of the squares of instantaneous values over a time interval (accumulation interval) and then performing a square root of the result after dividing by the number of samples in the interval . vx 2 vx 2 _sum vx_rms n instantaneous voltage (vx) n-1 n=0 x figure 18 . rms voltage computation
78m6610+lmu data sheet 29 rev 0 current ch annel measurements in addition to instantaneous current measurements updated every sample, peak current, rms current, and crest factor are updated every accumulation interval (n samples). register description time s cale ia ib instantaneous current 1 sample ia_peak ib_peak peak current 1 interval ia_rms ib_rms rms current ia_crest ib_crest current crest factor peak current this output is a capture of the largest magnitude instantaneous current load sample. ix_peak instantaneous current (ix) abs max maximum figure 19 . peak current computation
78m6610+lmu data sheet 30 rev 0 rms current the 78m6610+lmu reports true rms measurements for current inputs. the rms current is obtained by performing the sum of the squares of the instantaneous current samples over the accumulation interval and then performing a square root of the result after dividing by the number of samples in the interval . an optional rms offset for the current channels can be adjusted to reduce errors due to noise or system offsets (crosstalk) exhibited at low input amplitudes. full scale values in the i x rms_offs register s are squared and subtracted from the accumulated/divided squares. if the resulting rms value is negative, zero is used. ix 2 ix 2 _sum ix_rms n x instantaneous current (ix) n-1 n=0 ? ixrms_off 2 figure 20 . rms current computation minimum current the device includes a squelch feature to report zero current for no - load conditions . when the rms current value (checked at each accumulation interval) falls below the threshold ( irms_min ), the device will report zero current and prevent the continued accumulation of energy. register description irms_min if measured ix_rms is less than value in irms_min, then ix_rms is squelched and energy accumulation stops crest factor the crest factor outputs capture the result of the equation ix_crest = ix _peak / ix_rms for the most recent accumulation interva l . they have a range of 0 to 256.
78m6610+lmu data sheet 31 rev 0 power calculations this section describes the detailed flow of power calculations in the 78m6610+lmu . generic equations for ac power measurement are listed in the table below. register description time s cale pa pb instantaneous active power 1 sample pqa pqb instantaneous reactive power watt_a watt_b watt_c average active power (p) 1 interval var_a var_b var_c average reactive power (q) va_a va_b va_c apparent power (s) pfa pfb pfc power factor note: watt_c, var_c and va_c outputs are always scaled by a factor of 0.5. active power (p) the instantaneous power results (pa, pb) are obtained by multiplying aligned instantaneous voltage and current samples. the sum of these results are then averaged over n samples (accumulation time) to compute the average active power ( watt_ a, watt_ b), and the aggregate average power (watt_ c) . n n-1 n=0 n n-1 n=0 x vb ib + watt_a watt_b watt_c x va ia pa pb pb_offs if |x|< |y| z = 0 x y z pa_offs if |x|< |y| z = 0 x y z pa_sum pb_sum figure 21 . active power computation the value in the p x _off s register is the power offset for the power calculations. full scale values in the p x _offs register are subtracted from the magnitude of t he averaged active power. if the resulting active power value results in a sign change , zero watts are reported .
78m6610+lmu data sheet 32 rev 0 reactive power (q) instantaneous reactive power results (pqa, pqb) are calculated by multiplying the instantaneous samples of current and the instantaneous quadrature voltage . the sum of these results are then averaged over n samples (accumulation time) to compute the average reactive power (var_a, var_b), and the aggregate average reactive power (var_c) . a reactive power offset (q x _offs) is also provided for each channel . quadrature delay x n-1 n=0 ia va quadrature delay x n-1 n=0 ib vb + var_a var_b var_c pqa pqb vqa vqb q_offs if |x|< |y| z = 0 x y z q_offs if |x|< |y| z = 0 x y z n n pqa_sum pqb_sum figure 22 . reactive power computation apparent power (s) the apparent power, also referred as volt - amps, is the product of low - rate rms voltage and current results . offsets applied to rms current will affect apparent power results. x ia_rms va_rms va_a x ib_rms vb_rms va_b + va_c figure 23 . apparent power computation power factor ( pf) the power factor registers capture the ratio of active power to apparent power for the most recent accumulation interval . the sign of power factor is determined by the sign of active power. pfx = watt _x va _x
78m6610+lmu data sheet 33 rev 0 fundamental and harmonic calculations the 78m6610+lmu includes the ability to separate low - rate voltage, current, active power, and reactive power measurement results into fundamental and total harmonic components . these outputs can also be used to track individual harmonics as well as the total value excluding the selected harmonic. register description time s cale sine cosine instantaneous voltage of the internal waveform generator 1 sample vfund_a vfund_b voltage content at specified harmonic 1 interval ifund_a ifund_b current content at specified harmonic pfund_a pfund_b active power content at specified harmonic qfund_a qfund_b reactive power content at specified harmonic vharm_a vharm_b voltage content not at specified harmonic iharm_a iharm_b current content not at specified harmonic pharm_a pharm_b active power content not at specified harmonic qharm_a qharm_b reactive power content not at specified harmonic the harm register is used to select the single harmonic to extract. this input register is set by default to 0x000001 selecting the first harmonic (also known as the fundamental frequency) . this setting provides the user with fundamental result and the total harmonic distortion (thd) of the harmonics by setting the value in the harm register to a higher harmonic, the fundamental result registers will contain measurement results of the selected harmonic . likewise, by setting the value in the harm register to a higher harmonic, the harmonics result regis ters will report the measurement of the remaining harmonic s . as an example, for any given accumulation interval, the magnitude of measurement result ia_rms would be the sum of ifund_a and iharm_a. the sine and cosine registers are high - rate registers updated every sample with the instantaneous value of the respective outputs from the internal sine/cosine generator . the referenced ac voltage frequency serves as the reference for the internal waveform generator.
78m6610+lmu data sheet 34 rev 0 energy calculations energy calculations are included in the 78m6610 +lmu to minimize the traffic on the host interface and simplify system design . low - rate power measurement result s are multiplied by the number of samples (divisor) to calculate the energy in the last accumulation interval . energy r esults are summed together until a user defined bucket size is reached . when every bucket of energy is reached, the value in the energy counter register is incremented by one . all energy counter registers are low - rate 24 - bit output registers that contain values calculated over multiple accumulation intervals . both import (positive) and export (negative) results are provided for active and reactive energy. register description pa_pos_cnt pb_pos_cnt positive active energy counter pa_neg_cnt pb_neg_cnt negative active energy counter pqa_pos_cnt pqb_pos_cnt positive reactive energy counter pqa_neg_cnt pqb_neg_cnt negative reactive energy counter sa_cnt sb_cnt apparent energy counter energy results are cleared upon any power down or reset and can be manually cleared by the user using the control register . the cycles register can be used to detect device resets (loss of energy data) or to track time between energy reads . a bit in the status register also indicates when a reset has occurred. bucket size for energy counters the bucket register allows the user to define the unit of measure for the energy counter register s. it is an unsigned 48- bit fixed - point number with 24 bits for the integer part and 24 bits for the fractional part . high word low word bit position 23 22 2 1 0 . 23 22 21 20 1 0 value 2 2 3 2 2 2 2 2 2 1 2 0 2 - 1 2 - 2 2 - 3 2 - 4 2 - 2 3 2 - 2 4 the units should be set large enough to keep the accumulators and counters from overflowing too quickly . to increment the energy counters in watt - hours for example, the value in bucket should be equal to the number of seconds in an hour (3600) multiplied by the sample rate (4000) and divided by full scale watts (v f scale x i f scale). ???? ? ???? ( ?? ) = 3600 ? ? 4000 ? / ? ??????? ? ??????? full scale watts is defined by the sensors being used (see the scaling register s section) . as an example, if the voltage sources are 400 volts - peak at full scale (v f scale) and the current s are 30 amps - peak at full scale (i f scale), then full scale watts would be 12000 watts (v f scale x i f scale). the bucket value can be saved to flash memory as the register default .
78m6610+lmu data sheet 35 rev 0 example in this example the scaling registers are set as follows: vfscale = 667 (667v); ifscale = 50 (50a) in order to set the energy bucket to one wh: ?????? = 3600 ? 4000 667 ? 50 = 431 . 784 the value to enter in the bucket register should be set as: ?????? ???????? = 431 . 784 ? 2 24 the value to set the bucket register is therefore : high word = 0x0001af ; low word = 0xc8bb4c
78m6610+lmu data sheet 36 rev 0 min/max t racking the 78m6 6 10+lmu provide s a set of output register s for tracking the minimum and/or maximum values of up to six ( 6) different low - rate measurement results over multiple accumulation intervals . the user can select which measurements to track through an address table . mm_addr# uses word addressing for all host interface s. register description time scale mm_addr0 word a ddresses to track minimum and maximum values . a value of zero will disable tracking for that address slot . C mm_addr1 mm_addr2 mm_addr3 mm_addr4 mm_addr5 min0 minimum low - rate value at mm_addr# . multiple intervals min1 min2 min3 min4 min5 max0 maximum low - rate value at mm_addr# . multiple intervals max1 max2 max3 max4 max5 results are stored in ram and cleared upon any power down or reset and can be manually cleared using the control register . a bit in the status register is set whenever a min # or max# register is updated. the address values in mm_addr# can be saved to flash memory by the user as the register defaults. max# max maximum mm_addr# ram[#] min# min minimum control figure 24 . min/max tracking
78m6610+lmu data sheet 37 rev 0 alarm monitoring low -r ate a larm conditions are determined every accumulation interval . if results for die temperature, ac frequency, or rms voltage exceeds or drops below user configurable threshold s, then a respective alarm bit in the status register is set . for rms c urrent and watts r esults, maximum thresholds are provided for detecting over current or over power conditions with the load. register description t_ max threshold value which temperature must exceed to trigger alarm. t_ min threshold value which temperature must drop below to trigger alarm. f_ max threshold value which frequency must exceed to trigger alarm. f_ min threshold value which frequency must drop below to trigger alarm. v rms_max threshold value which rms voltage must exceed to trigger alarm. v rms_ min threshold value which rms voltage must drop below to trigger alarm . i rms_ max threshold value which rms current must exceed to trigger alarm. watt_ max threshold value which active power must exceed to trigger alarm. voltage sag and surge detection the 78m6610+lmu implements a voltage sag and surge detection function on both va and vb. the sag/surge detection function can generate an alarm when the line voltage drops below or exceeds the relevant programmable threshold s. the firmware calculates on a sample - by - sample basis the trailing mean square of the input voltage based on ? line cycle interval according to the following equation : ? ?? = ? ???? 2 ? ?????? ? ? ? 2 0 ?= ? ??? ( ? ?????? 2 ? ???? ) at each sample interval the v ms value is compared to a programmable threshold contained in the v sag and vsurge register s . if v ms falls below or r ise s above the relevant threshold s, the firmware sets the relevant bits in the alarms register. the sample count for sag detection is automatically adjusted by the firmware to maintain coverage over half of the ac line cycle. sag and surge detection is disabled by default and can be enabled by writing a non zero value to the vsag /vsurge register s . if the vsag /vsurge register s are set to 0, the sag/surge feature is disabled. the sag detection can be used to monitor or record the quality of the power line or utilize the sag a pin to notify external devices (for example a host microprocessor) of a pend ing power - down. the external device can then enter a power - down mode (for example saving data or recording the event) before a power outage. the f ollowing f igure shows a typical sag event.
78m6610+lmu data sheet 38 rev 0 sag_threshold figure 25 . voltage sag register description vsag_val t hreshold value (in rms) which voltage must go below to trigger a sag alarm . vsurg_val threshold value which voltage must go above to trigger alarm.
78m6610+lmu data sheet 39 rev 0 status registers the status regist er is used to monitor the status of the device and user configurable alarms . all other registers mentioned in this section share the same bit descriptions. the sticky register determines which alarm/status bits are sticky and which track the current status of the condition . each alarm bit defined as sticky will (once triggered) hold its alarm status until the user clears it using the status_reset register . any sticky bit not set will allow the respective status bit to clear when the condition clears. the status_set and the status_reset registers allow the user to force s tatus bits on or off respectively without fear of affecting unintended bits. a bit set in the status_set register will set the respective bit in the status register and a bit set in the status_reset register will clear it . status_set and status_reset are both cleared after the status bit is set or reset . the following table lists the bit mapping for all the status related registers. b it name stick - abl e description 23 drdy no new low - rate results (data) ready 22 mmupd y es min/max update occurred 21 va _ sag y es voltage a sag condition detected 20 vb _ sag y es voltage b sag condition detected 19 sign _v a no sign of va 18 sign _v b no sign of vb 17 ov_temp y es temperature over high limit 16 un_temp y es under low temperature limit 15 ov_freq y es frequency over high limit 14 un_freq y es under low frequency limit 13 ov_v rms a y es rms voltage a over limit 12 un_v rms a y es rms voltage a under limit 11 ov_v rms b y es rms voltage b over limit 10 un_v rms b y es rms voltage b under limit 9 va_ surge y es voltage a surge condition detected 8 vb_ surge y es voltage b surge condition detected 7 ov_watt1 y es power 1 over limit 6 ov_watt2 y es power 2 over limit 5 ov_amp1 y es current 1 over limit 4 ov_amp2 y es current 2 over limit 3 xstate no crystal status 2 relay1 always relay 1 on 1 relay2 always relay 2 on 0 reset always set by device after any type of reset
78m6610+lmu data sheet 40 rev 0 digital io functionality the dio_ state register contains the current status of the dio s . the user can use this register to read the state of a dio (if configured as an input ) or control the state of the dio ( if configured as an output) . the dio_ dir register sets the direction of the pins, where 1 is input and 0 is output . if a dio defined as an input is unconnected, internal pull ups will assert the respective dio bit in the dio_state register . note: some pins are used as serial interface pins and may not be capable of user control . during reset, all dios are configured as inputs. dio bit spi uart i 2 c mask register 0 mp0 mask0 1 sp ck addr 0 addr 0 C 2 sdi rxd sdai C 3 sdo txd sdao C 4 mp4 mask4 5 ssb rs485 dir scl C 6 mp 6 addr 1 addr 1 mask6 7 mp7 mask7 8 ifc0 C 9 ifc1 C 10 mp10 mask10 11:23 reserved i nterface configuration pin s ( ifc0 , ifc1) and address pins ( mp6/addr1 , spck/addr0 ) are input pins sampled at the end of a reset to select the serial host interface and set device addresses (for i 2 c and uart modes) . if the ifc0 pin is low, the device will operate in the spi mode . otherwise, the state of ifc1 and the addr# pins determine the operating mode and device address . the se pin s must remain configured as an input if directly connect ing to gnd/v 3p3 . otherwise, it is recommended to use external pullup or pulldown resistors accordingly. dio polarity dio s configured as outputs are by default active low. the logic 0 state is on. this can be modified using the dio_pol register using the same bit definition as the dio_state register. any corresponding bit set in the dio_pol register will invert the same dio output so that it becomes active high.
78m6610+lmu data sheet 41 rev 0 multi p urpose (mp) pins the 78m6610+lmu provides five mask registers for signaling the status of any status bit to one of five m ulti p urpose (mp) dio pins . these mask registers have the same bit mapping as the status register. the user must first enable the respective mp pin as an output before the dio can be driven to its active state . pin name register description mp0 mask0 a combination of a bit set in both the status register and a mask register causes the assigned mp pin to be activated (default active - low) . mp4 mask4 mp 6 /addr 1 mask6 mp7 mask7 mp10 mask10 relay control if one of the relay bit s in a mask register is set, only the respective relay status bit in the status register will change the state of the assigned mp pin . two options are provided for controlling the state of the relay status bit: 1. manual control of relay status using the status_set and status_reset registers . 2. autonomous control determined by the state of other bits in the status and mask register . for example, if a mask register has the relay1 and va_surge bits set, a surge alarm on voltage source va would assert the relay1 status bit. the 78m6610+lmu includes a programmable delay for driving the mp pins from the mask register when the relay bit is set . the relay control logic allows setting a delay time (increments of 250 s ) for energizing (setting) and de - energizing (clearing) the relay pin relative to the zero crossing of the referenced voltage source . the time specified in the registers is expressed in number of high - rate samples . there is a pipeline delay of 1 sample introduced by the timers. registers description rya_ton ryb_ton relay turn - on delay following low - to - high transition of referenced voltage. rya_toff ryb_toff relay turn - off delay following high - to - low transition of referenced voltage. relay command line voltage ton _delay de-energized energized de-energized toff _delay figure 26 . relay timing
78m6610+lmu data sheet 42 rev 0 command register the command register is located at address 0x00. use this register to perform specific tasks such as saving coefficients and nonvolatile register default s into flash memory. it also allows initiation of integrated calibration routines . value (hex) description 00xxxx normal operation caxxxx calibration commands bdxxxx software reset accxxx flash access commands normal operation the general settings command allows the user to enable functions such as uart auto reporting, relay operations, and line lock mode etc. bit(s) value description 23:16 0x00 general settings command used during normal operation . 5 ll line lock 1 = lock to line cycle; 0 = independent. 4 tc enable die temperature (gain) compensation 1 = enable; 0 = disable (debug only) calibration command the calibration command starts the calibration process for the selected inputs. it is assumed that appropriate input signals are applied. when the calibration process completes, bits 23:16 are cleared along with bits associated with channels that calibrated successfully. when calibrating gain, any channels that failed will have their corresponding bit left set. when calibrating offset, the bit corresponding to the selected channels will remain set. bit(s) value description 23:16 0xca calibrate command. 14 s2 calibrate voltage for sensor 2 . 13 s0 calibrate voltage for sensor 0 . 12 s3 calibrate current for sensor 3 . 11 s1 calibrate current for sensor 1 . 10 t calibrate temperature. 9 o calibrate offset ( = 1) or gain ( = 0) . 5 ll lock sample period to line cycle. 4 tc enable die temperature (gain) compensation 1 = enable; 0 = disable (debug only) note : during calibration, the ?line - lock? bit should be set for best results.
78m6610+lmu data sheet 43 rev 0 save to flash command use the acc command to save to flash the calibration coefficients and defaults for nonvolatile registers. upon reset or power - on, the values stored in flash will become new system defaults. the following table describes the acc command bits: bit(s) value description 23:12 0xacc access command. 11:8 0x2 2: save defaults to flash memory for nv registers . 5 1 line lock bit. 4 tc enable die temperature (gain) compensation 1 = enable; 0 = disable (debug only). control register a control register is provided for resetting the tracked energy and min/max measurement values and for clearing energy results . control bit description 23:3 reserved for future use 2 clear energy accumulators and frame c ounter 1 clear energy counters 0 reset min/max tracking configuration register the config register described throughout s ection 2.1 allows the user to configure which sensor (slot) inputs are used for voltage and current measurements. this section summarizes the configuration bits available to the user. the t wo msb s select the reference voltage slot for deriving zero - crossing detection and line frequency. config[23:22] 00 01 10 11 voltage reference s0 s2 s0 - s2 s0+s2 the remaining bits configure which the sensor inputs are used to derive line voltages and load currents. config bits 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 multiplier m2 m0 m2 m0 m2 m0 m3 m1 m3 m1 source vc vb va ib ia there are four choices for every m value as shown below. see s ection 2.1 for more information. multiplier bits 00 01 10 11 m (multiplier) value -1 0 1 2
78m6610+lmu data sheet 44 rev 0 register access all user registers are contained in a 256 - word (24 - bits each) area of the on - chip ram and can be accessed through the uart, spi, or i 2 c interfaces. these registers are byte - addressable via the uart interface and word - addressable via the spi, and i 2 c interfaces . these registers consist of read (output), write (input), and read/write in the case of the command register . writing to reserved registers or to unspecified memory locations could result in device malfunction or unexpected results. data types the input and output registers have different data types, depending on their assignment and functions . the notation used indicates whether the number is signed, unsigned, or bit - mapped and the location of the binary point. int indicates a 24 - bit integer with a range of 0 to 16777215 typically used for counters or boolean registers with 24 independent bit values. s indicates a signed fixed - point value . . i ndicates a fixed - point number . nn i ndicates the number of bits to the right of the binary point. example: s.21 is a 24 - bit s igned fixed - point number with 21 fraction bits to the right of the binary point and a range of - 4.0 to 4 -2 - 21 bit position 23 22 21 . 20 19 18 17 ? 2 1 0 bit multiplier s ign bit (-2 2 ) 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 - 19 2 - 20 2 - 21 max value 0 1 1 1 1 1 1 1 1 1 1 min value 1 0 0 0 0 0 0 0 0 0 0
78m6610+lmu data sheet 45 rev 0 register locations use word addresses for i 2 c and spi interfaces and byte addresses for the ssi (uart) protocol. nonvolatile (nv) register defaults are indicated with a y . all other registers are initialized as described in the functional description. word addr byte addr register type nv description 0 0 command int y command register (see command register s ection) 1 3 fw date int firmware release date in hex format (0x00ymd d ) 2 6 mask0 int y status bit mask for mp0 pin 3 9 mask4 int y status bit mask for mp4 pin 4 c mask6 int y status bit mask for mp6 pin 5 f mask7 int y status bit mask for mp7 pin 6 12 mask10 int y status bit mask for mp10 pin 7 15 sticky int y status bits to hold until cleared by host 8 18 samples int y high - rate samples per low rate (default 400) 9 1b calcycs int y number of calibration cycles to average a 1e phasecomp1 s.21 y phase compensation (+/ - 4 samples) for s1 input b 21 phasecomp 3 s.21 y phase compensation (+/ - 4 samples) for s3 input c 24 s1_gain s.21 y input s 1 gain calibration. positive values only d 27 s0_gain s.21 y input s0 gain calibration. positive values only e 2a s3_gain s.21 y input s3 gain calibration. positive values only f 2d s2_gain s.21 y input s2 gain calibration. positive values only 10 30 s1_offs s.23 y input s0 offset calibration 11 33 s0_offs s.23 y input s 1 offset calibration 12 36 s3_offs s.23 y input s3 offset calibration 13 39 s2_offs s.23 y input s 2 offset calibration 14 3c t_gain s.10 y temperature slope calibration 15 3f t_offs s.10 y temperature offset calibration 16 42 hpf_coef_i s.23 y current input hpf coefficient . positive values only 17 45 hpf_coef_v s.23 y voltage input hpf coefficient . positive values only 18 48 vsurg_int int y voltage surge detect interval 19 4b vsag_int int y voltage sag detect interval 1a 4e status int alarm and device status bits 1b 51 status_set int used to set status bits 1c 54 status_reset int used to reset status bits 1d 57 dio_state int state of dio pins 1e 5a cycle int high - rate sample counter 1f 5d frame int 48 bit low - rate sample number C low word 20 60 frame int 48 bit low - rate sample number C high word 21 63 divisor int actual samples in previous low - rate period 22 66 harm int harmonic selector, default: 1 (fundamental) 23 69 devaddr int y high order address bits for i 2 c and uart interfaces 24 6c control int control (see text) 25 6f config int y input source m (gain) selectors and more 26 72 vtarget s .23 y voltage calibration target . positive values only 27 75 vsurg_ val s .23 y voltage surge threshold . positive values only 28 78 vsag_ val s .23 y voltage sag threshold . positive values only
78m6610+lmu data sheet 46 rev 0 word addr byte addr register type nv description 29 7b v rms_ min s .23 y voltage lower alarm limit . positive values only 2a 7e v rms_ max s .23 y voltage upper alarm limit . positive values only 2b 81 va_rms s .23 rms voltage for va source 2c 84 vb_rms s .23 rms voltage for vb source 2d 87 va_fund s.23 fundamental voltage for va source 2e 8a vb_fund s.23 fundamental voltage for vb source 2f 8d va_harm s.23 harmonic voltage for va source 30 90 vb_harm s.23 harmonic voltage for vb source 31 93 vc_rms s . 23 rms voltage for vc source 32 96 C s.23 reserved output 33 99 va s.23 instantaneous voltage for va source 34 9c vb s.23 instantaneous voltage for vb source 35 9f vqa s.23 instantaneous quadrature voltage for va source 36 a2 vqb s.23 instantaneous quadrature voltage for vb source 37 a5 vc s.23 instantaneous voltage for vc source 38 a8 sine s.23 reference sine 39 ab cosine s.23 reference cosine 3a ae va_peak s.23 peak recorded voltage 3b b1 vb_peak s.23 peak recorded voltage 3c b4 itarget s .23 y current calibration target . positive values only 3d b7 irms_min s .23 y rms current to squelch as zero. positive values only 3e ba ia_rms s .23 rms current for ia source 3f bd ib_rms s .23 rms current for ib source 40 c0 ia_fund s.23 fundamental current for ia source 41 c3 ib_fund s.23 fundamental current for ib source 42 c6 ia_harm s.23 harmonic current for ia source 43 c9 ib_harm s.23 harmonic current for ib source 44 cc ia s.23 instantaneous current for ia source 45 cf ib s.23 instantaneous current for ib source 46 d2 ia_peak s.23 peak recorded voltage 47 d5 ib_peak s.23 peak recorded voltage 48 d8 irms_ max s .23 y over current alarm limit . positive values only 49 db i a rms_offs s .23 y rms current offset for ia . positive values only 4a de i b rms_offs s .23 y rms current offset for ib . positive values only 4b e1 watt_a s.23 active power for source a 4c e4 watt_b s.23 active power for source b 4d e7 watt_c s.2 3 total active power 4e ea va_a s.23 volt - amperes for source a 4f ed va_b s.23 volt - amperes for source b 50 f0 va_c s.23 total volt - amperes 51 f3 var_a s.23 reactive power for source a 52 f6 var_b s.23 reactive power for source b 53 f9 var_c s.23 total reactive power 54 fc p fund _a s.23 fundamental active power for source a 55 ff p fund _b s.23 fundamental active power for source b 56 102 p harm _a s.23 harmonic active power for source a 57 105 p harm _b s.23 harmonic active power for source b
78m6610+lmu data sheet 47 rev 0 word addr byte addr register type nv description 58 108 q fund _a s.23 fundamental reactive power for source a 59 10b q fund _b s.23 fundamental reactive power for source b 5a 10e q harm _a s.23 harmonic reactive power for source a 5b 111 q harm _b s.23 harmonic reactive power for source b 5c 114 pa s.23 instantaneous active power for source a 5d 117 pb s.23 instantaneous active power for source b 5e 11a pqa s.23 instantaneous reactive power for source a 5f 11d pqb s.23 instantaneous reactive power for source b 60 120 watt_ max s .23 y power alarm limit 61 123 p a _offs s .23 y active power offset for pa . positive values only 62 126 q a _offs s .23 y reactive power offset for pqa . positive values only 63 129 p b _offs s .23 y active power offset for pb. positive values only 64 12c q b _offs s .23 y reactive power offset for pqb . positive values only 65 12f pfa s.22 source a power factor 66 132 pfb s.22 source b power factor 67 135 pfc s.22 total power factor 68 138 C int reserved input 69 13b tempc s. 10 chip temperature 6a 13e t_target s. 10 y temperature calibration target 6b 141 t_min s. 10 y temperature lower alarm limit 6c 144 t_max s. 10 y temperature upper alarm limit 6d 147 freq s.16 line frequency 6e 14a f_min s.16 y line frequency lower alarm limit 6f 14d f_max s.16 y line frequency upper alarm limit 70 150 C int reserved input 71 153 min1 minimum recorded value 1 72 156 min2 minimum recorded value 2 73 159 min3 minimum recorded value 3 74 15c min4 minimum recorded value 4 75 15f min5 minimum recorded value 5 76 162 min6 minimum recorded value 6 77 165 max1 maximum recorded value 1 78 168 max2 maximum recorded value 2 79 16b max3 maximum recorded value 3 7a 16e max4 maximum recorded value 4 7b 171 max5 maximum recorded value 5 7c 174 max6 maximum recorded value 6 7d 177 mm_addr1 int y min/max monitor - word a ddress 1 7e 17a mm_addr2 int y min/max monitor - word a ddress 2 7f 17d mm_addr3 int y min/max monitor - word a ddress 3 80 180 mm_addr4 int y min/max monitor - word a ddress 4 81 183 mm_addr5 int y min/max monitor - word a ddress 5 82 186 mm_addr6 int y min/max monitor - word a ddress 6 83 189 vfscale int y (see scaling register s section) 84 18c ifscale int y (see scaling register s section) 85 18f scratch1 int y extra register for storing user info 86 192 scratch2 int y extra register for storing user info
78m6610+lmu data sheet 48 rev 0 word addr byte addr register type nv description 87 195 scratch3 int y extra register for storing user info 88 198 scratch4 int y extra register for storing user info 89 19b bucket int y energy bucket size C low word 8a 19e bucket int y energy bucket size C high word 8b 1a1 ia_crest s.16 crest factor for ia (positive values only) 8c 1a4 ib_crest s.16 crest factor for ib (positive values only) 8d 1a7 C int reserved output 8e 1aa C int reserved output 8f 1ad pa_pos_cnt int positive active energy counter 90 1b0 C int reserved output 91 1b3 C int reserved output 92 1b6 pa_neg_cnt int negative active energy counter 93 1b9 C int reserved output 94 1bc C int reserved output 95 1bf pb_pos_cnt int positive active energy counter 96 1c2 C int reserved output 97 1c5 C int reserved output 98 1c8 pb_neg_cnt int negative active energy counter 99 1cb C int reserved output 9a 1ce C int reserved output 9b 1d1 pqa_pos_cnt int leading reactive energy counter 9c 1d4 C int reserved output 9d 1d7 C int reserved output 9e 1da pqa_neg_cnt int lagging reactive energy counter 9f 1dd C int reserved output a0 1e0 C int reserved output a1 1e3 pqb_pos_cnt int leading reactive energy counter a2 1e6 C int reserved output a3 1e9 C int reserved output a4 1ec pqb_neg_cnt int lagging reactive energy counter a5 1ef C int reserved output a6 1f2 C int reserved output a7 1f5 sa_cnt int apparent energy counter a8 1f8 C int reserved output a9 1fb C int reserved output aa 1fe sb_cnt i24 apparent energy counter ab 201 rya_ton i24 y relay #1 turn - on delay ac 204 ryb_ton i24 y relay #2 turn - on delay ad 207 rya_toff int y relay #1 turn - off delay ae 20a ryb_toff int y relay #2 turn - off delay af 20d rya_cnt int delay count for relay #1 b0 210 ryb_cnt int delay count for relay #2 b1 213 baud int y baud rate for uart interface b2 216 dio_pol int y polarity of dio pins . 1 = active high ; 0 = active low b3 219 dio_dir int y direction of dio pins . 1 = input ; 0 = output
78m6610+lmu data sheet 49 rev 0 s erial interfaces all user registers are contained in a 256 - word (24 - bit s each ) area of the on - chip ram and can be accesse d through the uart, spi , or i 2 c interfaces. while access to a single byte is possible with some interfaces, it is highly recommended that the user access words (or multiple words) of data with each transaction. only one interface can be active at a time . the interface selection pins are sampled at the end of a reset sequence to determine the operating mode. the user should allow 10ms from a power - up or reset event to provide the firmware adequate time to sample the state of these pins. during this time the status of these pins must not change. interface mode ifc0 ifc1 spi 0 x (dont care) uart 1 0 i 2 c 1 1 uart interface the device implements a simple serial interface (ssi) protocol on the uart interface that features: ? support for s ingle and multipoint communications ? transmit ( direction ) control for an rs - 485 transceiver ? e fficient use of a low bandwidth serial interface ? data integrity checking the default configuration is 38400 baud, 8 - bit, no - parity, 1 stop - bit, no flow control. the value in the baud register determines the baud rate to be used . example: to select a 9600 baud rate, the user writes a decimal 9600 to the baud register. the new rate will not take effect immediately. it must be saved to flash and will take effect at the next reset. the maximum baud value is 115200. rs - 485 support the ssb/dir/scl pin is used to drive a n rs - 485 transceiver output enable or direction pin. the implemented protocol supports a full - duplex 4- wire rs - 485 bus . rs-485 bus a b rout ren den din 78m6610+lmu sdi/rx/sdai ssb/dir/scl sdo/tx/sdao 4.7k a b rs-485 bus figure 27 . rs - 485 interface
78m6610+lmu data sheet 50 rev 0 device address configuration the ssi protocol utilizes 8 - bit addressing for multipoint communications. the usable ssi id range is 1 to 255. in multipoint systems with more than 4 targets, the user must configure device address bits in the devaddr according to the formula ssi id = device address +1 and save the values to flash memory as the default. a change in the device address takes effect following a power - on or reset. during the initialization, the devaddr register value is restored from flash memory and the state of the address pins are acquired. a device address of 'ff' is not supported. devaddr [23:6] bits are not used and have no effect on the device address. 7 6 5 4 3 2 1 0 devaddr register bit 5:0 mp6/addr1 pin spck/addr0 pin device address ssi id = device address +1 figure 28 . device address configuration
78m6610+lmu data sheet 51 rev 0 ssi protocol description t he ssi protocol is command response system supporting a single master and one or more targets . the host ( master ) sends commands to a selected target that first verifies the integrity of the packet before sending a reply or executing a command . failure to decode a host packet will cause the selected target to send a fail code. if the condition of a received packet is uncertain, no reply is sent . each target must have a unique ssi id. zero is not a valid ssi id for a target device as it is used by the host to de - select all target devices . with both address pins low on the 78m6610+lmu , the ssi id defaults to 1 and is the selected device following a reset . this configuration is intended for s ingle target (point - to - point) systems that do not require the use of device addressing or selecting targets . in multipoint systems , t he master will typically de- select all target devices by selecting ssi id #0 . the master must then select the target with a valid ssi id and get an acknowledgement from the slave before set ting the targets register address pointer and performing read or write operations. if no target is selected , no reply is sent . the ssb/dir/scl pin is asserted while the device is selected . the sequence of operation is shown in the following diagram. select target device set register address pointer read/write commands de-select target device figure 29 . ssi protocol master packets master p ackets always start with the 1- byte header (0xaa) for synchronization purposes . t he master then sends the byte count of the entire packet (up to 255 byte packets) followed by the payload (up to 253 bytes) and a 1- byte modulo - 256 check sum of all packet bytes for data integrity check ing . header (0xaa) byte count checksum payload figure 30 . master packet structure the payload can contain either a single command or multiple commands if the target is already selected . it can also include device address es, register addresses , and data. a ll multi byte payloads are sent and received least - significant - byte first .
78m6610+lmu data sheet 52 rev 0 master packet command summary command parameters description 0 - 7f (invalid) 80 - 9f (not used) a0 clear address a1 [byte - l] set read/write address bits [7:0] a2 [byte - h] set read/write address bits [15:8] a3 [byte - l][byte - h] set read/write address bits [15:0] a4 - af (reserved for larger address targets) b0 - bf (not used) c0 de - select target (target will acknowledge) c1 - ce select target 1 to 14 (target will acknowledge) cf [byte] select target 0 to 255 (target will acknowledge) d0 [data...] write bytes set by remainder of byte count d1 - df [data...] write 1 to 15 bytes e0 [byte] read 0 to 255 bytes e1 C ef read 1 to 15 bytes f0 - ff (not used) users only need to implement commands they actually need or intend to use. for example, only one address command is required C either 0xa1 for systems with 8 address bits or less or 0xa3 for systems with 9 to 16 address bits. likewise, only one write, read, or select target command needs to be implemented. select target is not needed in systems with only one target.
78m6610+lmu data sheet 53 rev 0 command payload examples device selection payload 0xcf command ssi id register address pointer selection payload 0xa3 command register a ddress (2 bytes) small read command (3 bytes) payload 0xe3 command large read command (30 bytes) payload 0xe0 command 0x1e ( 30 bytes) small write command (3 bytes) payload 0xd3 command 3 bytes of dat a large write command (30 bytes) byte count payload 0x21 (3 4 bytes) 0xd0 command 30 bytes of dat a after each read or write operation, the internal address pointer is incremented to point to the address that followed the target of the previous read or write operation.
78m6610+lmu data sheet 54 rev 0 slave packets the type of slave packet depends upon the type of command from the master device and the successful execution by the slave device . standard replies include acknowledge and acknowledge with data . acknowledge without data acknowledge with data byte count read data check sum if no data is expected from the slave or there is a fail code, a single byte reply is sent . if a successfully decoded command is expected to reply with data, the slave sends a packet format similar to the master packet where the header is replaced with a reply code and the payload contains the read data. reply code definition 0xaa acknowledg e with data 0xab acknowledge with data (half duplex) 0xad acknowledge without data. 0xb0 negative acknowledge (nack). 0xbc command not implemented. 0xbd checksum failed. 0xbf buffer overflow (or packet too long). - timeout - any condition too difficult to handle with a reply. failure to decode a host packet will cause the selected target to send a fail code (0xb0 C 0xbf) acknowledgement depending on mode of failure. masters wishing to simplify c ould accept any unimplemented fail code as a negative acknowledge . if no target is selected or the condition of a received packet is uncertain, no reply is sent. timeouts can also occur when data is corrupt or no target is selected. the master should implement the appropriate timeout control logic after approximately 50 byte times at the current baud rate . when a first reply byte is received, the master should check to see if it is an ssi header or an acknowledge. if so, the timeout timer is reset, and each subsequent receive byte will also reset the timer. if no byte is received within the timeout interval, the master can expect the slave timed out and re - send a new command.
78m6610+lmu data sheet 55 rev 0 spi interface the 78m6610+lmu spi can be configured as slave only. once the spi interface is activated, it utilizes the following pins: ssb: slave select (ss) is an input and active low signal sck: serial data clock (sck) input sdo: ma ster input/slave output (miso), serial data output sdi: master output/slave input (mosi), serial data input clock polarity and phase the figure below shows a single - byte transaction on the spi bus . the data is shifted on the falling edge of the serial data clock and latched (captured) on the rising edge. sck msb 6 5 4 3 2 1 msb 6 5 4 3 2 1 lsb lsb sdi (master output) sdo (master input) ssb (to slave) figure 31 . spi interface spi protocol the spi allows access to the 78m6610+lmu registers. the first byte that the master needs to tran smit to the 78m6610+lmu (slave) is the control byte . the control byte allows setting the number of words to be transferred and the most significant bits of the register address : bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n bracc [3:0] addr7 addr6 0 1 addr7 and addr6 bits select bit 7 and 6 of the 8 - bit register address to be accessed by the fo llowing data transactions. the read and write register are contained in a 256 w ords ( 24 - bit) area of the on - chip ram. nbracc[3:0] represents the number of words (3 - bytes) accesses to be performed by subsequent data transactions . the actual number of data addresses accessed per data transaction is nbracc + 1 . for single address access, the field is set at 0 . nbracc is reset to 0 when the operation (multiple reads or writes) is completed . nbracc must be set to a nonzero value prior to each multiple word transaction.
78m6610+lmu data sheet 56 rev 0 the second type of transaction is dedicated to transporting data between the host and the device and is structured as follows: byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 addr[5:0] r/w 0 2 data[23:16] @ addr 3 data[15:8] @ addr 4 data[7:0] @ addr 5 data[23:16] @ addr + 1 6 data[15:8] @ addr +1 7 data[7:0] @ addr +1 (nbracc *3) data[7:0] @ addr + nbracc (nbracc*3)+1 data[23:16] @ addr + nbracc (nbracc*3)+2 data[15:8] + nbracc (nbracc*3)+3 data[7:0] + nbracc r/w: defines the directionality of the transaction (read = 0; write = 1); addr[5:0]: indicates the remainder of the address to access. the following are some transaction examples. example 1: write access of address 0x14. byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 nbracc[3:0] = 0x00 addr7 = 0 addr6 = 0 0 1 2 addr[5:0] = 0x14 wr = 1 0 3 data[23:16] @ 0x14 4 data[15:8] @ 0x14 5 data[7:0] @ 0x14 example 2: read access of address 0x17 and 0x18. byte number bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 nbracc[3:0] = 0x01 addr7 = 0 addr6 = 0 0 1 2 addr[5:0] = 0x17 rd = 0 0 3 data[23:16] @ 0x17 4 data[15:8] @ 0x17 5 data[7:0] @ 0x17 6 data[23:16] @ 0x18 7 data[15:8] @ 0x18 8 data[7:0] @ 0x18
78m6610+lmu data sheet 57 rev 0 example 3: non c ontiguous read accesses of address 0x17 and 0x0a. byte# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 nbracc[3:0] = 0x00 addr7 = 0 addr6 = 0 0 1 2 addr[5:0] = 0x17 rd = 0 0 3 data[23:16] @ 0x17 4 data[15:8] @ 0x17 5 data[7:0] @ 0x17 6 nbracc[3:0] = 0x00 addr7 = 0 addr6 = 0 0 1 7 addr[5:0] = 0x0a w = 1 0 8 data[23:16] @ 0x0a 9 data[15:8] @ 0x0a 10 data[7:0] @ 0x0a the timing of the transaction can be organized in different ways depending on the host capabilities . the above transaction can be a succession of bytes as shown in the diagram below . those bytes are carried by a continuously active sck, with eight clock periods per byte. byte 2: addr & ctrl byte 4: data[15:8] byte 5: data[7:0] sdi byte 3: data[23:16] byte 1: control sck active sck sdo ssb hiz figure 32 . spi timing continuous clock the host also has the possibility to space out the bytes transmitted . in such a case, sck is inactive during the in - between - bytes gap, as illustrated below . note that the figure shows two gaps, one between the configuration and the data transactions and another between bytes within the data transaction . the placement of those gaps is strictly for the purpose of illustrating the concept. byte 2: addr & ctrl byte 4: data[15:8] byte 5: data[7:0] sdi byte 3: data[23:16] byte 1: control sck active sck sdo ssb hiz sck active sck active figure 33 . spi timing gapped clock
78m6610+lmu data sheet 58 rev 0 i 2 c interface the 78m6610+lmu has an i 2 c interface available at the sdai, sdao, and scl pins. the interface supports i 2 c slave mode with a 7 - bit address and operates at a data rate up to 400khz. the figure below shows two possible configurations. configuration a is the standard configuration. the double pin for sda also allows for isolated configuration b. v 3p3 or 5vdc sdai sdao 5vd c i2c_gnd sck sdai sdao sck a) standard configuration b) isolated configuration 5vdc sda sck sda sck v 3p3 or 5vdc v 3p3 or 5vdc figure 34 . i 2 c interface device address configuration by default, there are only four possible addresses for the max78615+lmu as defined by two external address pins. to expand the potential address of the device to the entire 7 - bit address range for i 2 c, one can set i 2 c address bits 6 through 2 in the devaddr register and save them to flash memory as the default. a change in the device address takes effect following a power - on or reset. during the initialization, the devaddr register value is restored from flash memory and the state of the address pins are acquired. devaddr bits 23 through 5 are not used and have no effect on the device address. 6 5 4 3 2 1 0 devaddr register bit 4:0 spck/addr0 pin mp6/addr1 pin i 2 c device address figure 35 . i 2 c device address
78m6610+lmu data sheet 59 rev 0 bus characteristics ? a d ata transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. bus conditions: ? bus n ot busy (i): both data and clock lines are high indicating an idle condition . ? start data transfer (s): a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. ? stop data transfer (p): a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. ? data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. ? acknowledge (a): each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge - related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. i n this case, the slave (78m6610 +lmu ) will leave the data line high to enable the master to generate the stop condition. 1 2 7 8 9 ack msb start bit start or stop bits scl may be held low by slave to service interrupts scl sda 9 ack figure 36 . i 2 c bus characteristics device addressing a control byte is the first byte received following the start condition from the master device. the control byte consists of a seven bit address and a bit (lsb) indicating the type of access (0 = write; 1 = read). s x x x r/w x x x x ack start bit device address lsb msb read/write acknowledge figure 37 . i 2 c device addressing
78m6610+lmu data sheet 60 rev 0 write operations following the start (s) condition from the master, the device address (7 - bits) and the r/ w bit (logic low for write) are clocked onto the bus by the master . this indicates to the addressed slave receiver that the register address will follow after it has generated an acknowledge bit (a) during the ninth clock cycle . therefore, the next byte transmitted by the master is the register address and will be written into the address pointer of the 78m 6610 +lmu . after recei ving another acknowledge (a) signal from the 78m 6610 +lmu , the master device will transmit the data byte(s) to be written into the addressed memory location . the data transfer end s when the master generates a stop (p) condition. this initiates the internal write cycle . the example below shows a 3 - byte data write (24 - bit register write). s device address 65 43 210 0 s t a r t a c k register address 5 43 210 6 7 a c k data 1 2 3 4 5 6 7 a c k 0 p s t o p data 1 2 3 4 5 6 7 0 data 1 2 3 4 5 6 7 0 a c k a c k figure 38 . write operation single register upon receiving a stop (p) condition, the internal register address pointer will be incremented . the write access can be extended to multiple sequential registers. the figure below shows a single transaction with multiple register s written sequentially. s device address 65 43 210 0 s t a r t a c k register address (n) 5 43 210 6 7 a c k data 1 2 3 4 5 6 7 a c k 0 p data 1 2 3 4 5 6 7 0 data 1 2 3 4 5 6 7 0 a c k a c k register (n) 2 3 4 1 0 register (n+1) 6 7 a c k 2 3 4 1 0 6 7 a c k register (n+2) register (n+x) figure 39 . write operation multiple registers
78m6610+lmu data sheet 61 rev 0 read operations read operations are initiated in the same way as write operations with the exception that the r/ w bit of the control byte is set to one . there are two basic types of read operations: current address read and random read. current address read: the 78m 6610 +lmu contains an address counter that maintains the address of the last register accessed, internally incremented by one when the stop bit is received . therefore, if the previous read access was to register address n, the next current address read operation would access data from address n + 1. upon receipt of the control byte with r/ w bit set to one, the 78m 6610+lmu issues an acknowledge ( a) and transmits the eight bit data byte . the master will not acknowledge the transfer, but generates a stop condition to end the transfer and the 78m 6610+lmu will discontinue the transmission. s device address 65 43 210 1 s t a r t a c k data 1 2 3 4 5 6 7 a c k 0 p s t o p data 1 2 3 4 5 6 7 0 data 1 2 3 4 5 6 7 0 a c k n o a c k figure 40 . read operation this read operation is not limited to 3 bytes but can be extended until the register address pointer reaches its maximum value . if the register address pointer has not been set by previous operations, it is necessary to set it issuing a command as follows: s device address 0 1 2 3 4 5 6 0 s t a r t a c k register address (n) 2 3 4 5 6 7 s 1 0 a c k p s t o p figure 41 . setting read address random read: random read operations allow the master to access any register in a random manner. to perform this operation, the register address must be set as part of the write operation. after the address is sent, the master generates a start condition following the acknowledge response. this sequence completes the write operation. the master should issue the control byte again this time, with the r/ w bit set to 1 to indicate a read operation. the 78m6610 +lmu will issue the acknowledge response, and transmit the data . at the end of the transaction the master will not acknowledge the transfer and generate a stop condition. s device address 0 1 2 3 4 5 6 0 s t a r t a c k register address (n) 2 3 4 5 6 7 s 1 0 a c k s r device address 0 1 2 3 4 5 6 1 s t a r t a c k data 5 4 3 2 1 0 6 7 s n o a c k data 1 2 3 4 5 6 7 a c k 0 data 1 2 3 4 5 6 7 0 a c k figure 42 . reading multiple registers this read operation is not limited to 3 bytes but can be extended until the register address pointer reaches its maximum value.
78m6610+lmu data sheet 62 rev 0 ordering information part temp range pin - package top mark 78m6610+lmu/b01 - 40 c to +85 c 24 - t qfn emp 78m6610+lmu/b01t - 40 c to +85 c 24 - t qfn emp + denotes a lead(pb) - free/rohs - compliant package. t = tape and reel. contact information for more information about the 78m6610+lmu or other maxim integrated products , go to: www.maximintegrated.com/support .
78m6610+lmu data sheet maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in t his data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1 - 408- 601- 1000 63 ? 201 3 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history r evision number r evision date d escription pages changed 0 1/13 initial release

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